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Ben Meadors
25996e9330
* Fix W12 battery reading: add ADC_CTRL and correct the divider ratio
The W12 battery config was taken from the vendor's Demo_06_ADC_Read.ino,
which reads GPIO1, multiplies by 2.0 under a literal "Assumption: 2:1
voltage divider" comment, and never touches the ADC enable at all. All
three of those details are wrong.
Schematic W12-MB-V0.2 sheet 1 has the divider behind a P-MOSFET high-side
switch so it only draws from the cell during a reading:
BAT --S[Q6 AO3401A]D-- R50 390K --IO1_ADC_IN-- R51 100K -- GND
|G R49 1K to BAT (gate pull-up: Q6 off by default)
+-- R48 1K -- C[Q7 S8050 NPN]E -- GND, base <- R52 1K <- IO2
So GPIO2 is ADC_CTRL, not "a second (solar/VUSB) divider" as the variant
claimed, and the NPN inverts it, making it active HIGH. Left undriven, Q6
stays off and GPIO1 sits at ground through R51 - a hard 0 raw rather than
the 100-250mV of noise a floating pin gives - so every boot reported
"battery hardware absent (USB-only)" and battery_level 101.
The divider is 390K/100K, so the multiplier is 4.9, not 2.0. That puts a
4.2V cell at only ~857mV on the pin, so drop the attenuation from the
12dB default (0-3100mV) to 2.5dB (0-1250mV) to use the range properly.
This matches the Heltec V3/V4 network, but their ADC_CTRL 37 cannot be
reused here: GPIO33-37 are consumed by this board's octal PSRAM.
Verified on hardware: reports 4067mV / 91%, stable to the mV across
consecutive samples, where it previously read 0mV with a cell attached.
* Trim the battery comment block to house style
Per the repo guideline that code comments stay to one or two lines and
avoid multi-paragraph blocks, drop the ASCII schematic from the header.
The full circuit trace lives in the previous commit message and the PR
description, which is where that rationale belongs.
Comment-only; both define values are unchanged.
51 lines
2.9 KiB
C
51 lines
2.9 KiB
C
#pragma once
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// Meshnology W12 "WiFi LoRa 32 V5" - ESP32-S3R8 (8 MB PSRAM) + 16 MB flash + Semtech LR2021
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// dual-band LoRa (sub-GHz + 2.4 GHz) + SSD1315 0.96" OLED. Heltec V3-style pinout.
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// ─── OLED ─────────────────────────────────────────────────────────────────────
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// SSD1315 (SSD1306-compatible) 128x64 at 0x3C
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#define USE_SSD1306
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#define I2C_SDA 17
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#define I2C_SCL 18
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#define BICOLOR_OLED_DISPLAY
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// Powers the OLED/peripheral rail; active LOW
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#define VEXT_ENABLE 45
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// ─── User input ───────────────────────────────────────────────────────────────
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#define BUTTON_PIN 0 // BOOT doubles as user button
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// ─── Battery ──────────────────────────────────────────────────────────────────
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// GPIO2 gates a P-MOSFET high-side switch on the divider (schematic W12-MB-V0.2 sheet 1); an NPN
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// inverts it, so it is active HIGH. Undriven, the switch stays off and GPIO1 reads a hard 0 mV.
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#define BATTERY_PIN 1
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#define ADC_CHANNEL ADC_CHANNEL_0 // GPIO1 = ADC1_CH0
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#define ADC_CTRL 2
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#define ADC_CTRL_ENABLED HIGH
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#define ADC_ATTENUATION ADC_ATTEN_DB_2_5 // 4.2V cell is only ~857mV after the divider
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#define ADC_MULTIPLIER (490.0 / 100.0) // R50 390K + R51 100K, over R51
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// ─── LoRa radio ───────────────────────────────────────────────────────────────
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// RF switching is hardwired to the radio's CTX/CPS pins, and the external PA enables
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// (IO3 sub-GHz, IO4 2.4GHz) are pulled high, so no RF-switch DIO table is needed.
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#define USE_LR2021
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#define LORA_SCK 9
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#define LORA_MISO 11
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#define LORA_MOSI 10
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#define LORA_CS 8
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#define LORA_DIO1 14 // radio DIO8; also the LoRa sleep-wake pin
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#define LR2021_SPI_NSS_PIN LORA_CS
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#define LR2021_IRQ_PIN LORA_DIO1
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#define LR2021_NRESET_PIN 12
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#define LR2021_BUSY_PIN 13
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// Must be 8, not RadioLib's default of 5: DIO5 is not bonded out here, so the default
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// points every interrupt at a floating pin and scanChannel() never returns.
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#define LR2021_IRQ_DIO_NUM 8
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// DIO7 -> IO7 is a second, unused IRQ line. Plain crystal on XTA/XTB, so no TCXO voltage.
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// ─── Not wired up yet ─────────────────────────────────────────────────────────
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// RGB LED on GPIO46 stays off: HAS_NEOPIXEL pulls in the RMT HAL, which fails to link here.
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// L76K GNSS header (RX=39, TX=38, CTRL=48 active low, WAKE=40, PPS=41, RST=42) is unpopulated.
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