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https://github.com/alexhopeoconnor/firmware.git
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Ben Meadors
12b2d973a4
* Right-size nRF52 heap tiers after 2.8.0 heap-exhaustion field reports Field reports on 2.8.0 show nRF52840 devices at 99% heap (114/115 KB) within minutes of boot; operator new asserts on OOM, so these devices are one allocation from a reboot. The 2.8.0 cache sizing ladders gave nRF52 the largest non-PSRAM tiers on the assumption that a BLE-only part has a roomy heap - the arena is actually ~125 KB shared with the FreeRTOS task stacks. Per-target retiers (nRF52840 unless noted): - Traffic Management cache 1000 -> 250 entries (10 KB -> 2.5 KB); the unclassified fallthrough drops 1000 -> 400 to match the classic-ESP32 tier (also affects RP2040/RP2350) - Warm node store 200 -> 100 entries (8 KB -> 4 KB); the non-XXAA fallthrough drops 320 -> 100 so an unclassified RAM-constrained part can't boot-allocate 12.8 KB - MESSAGE_HISTORY_LIMIT 20 -> 10 (text pool 4.4 KB -> 2.2 KB), the tier classic ESP32 already ships - MAX_RX_TOPHONE 32 -> 16, shrinking the static packet pool 70 -> 54 slots (~6.6 KB of .bss returned to the heap arena) - PacketHistory hash index off arch-wide (1 KB); O(n) over 240 records is negligible at LoRa packet rates - OLEDDISPLAY_REDUCE_MEMORY arch-wide (~1 KB OLED back buffer); the five TFT variants -U it because TFTDisplay.cpp needs buffer_back for dirty-window diffing - Drop the stale "for testing" 1024-entry TMM override on T1000-E Measured on rak4631: heap arena grows 124,572 -> 131,180 B and boot allocations drop ~15.7 KB, roughly +22 KB free heap on the field-report device class. Migration: the nRF52840 warm flash ring replays through place() (LRU), so the newest 100 identities survive the shrink; the file backend rejects oversized snapshots cleanly (new test covers this). Native suites pass (536/536 Docker, 13/13 native-macos warm store); rak4631, heltec-mesh-node-t114 (TFT) and tracker-t1000-e build green. * Add central memory-class ladder (MemClass.h) with fail-safe-small defaults The 2.8.0 nRF52840 heap exhaustion happened because each RAM-sized cache picked its per-platform tier from its own chip #ifdef ladder, and every ladder's fallthrough default was its largest non-PSRAM tier - nRF52 was never named, so it silently got 1000-entry caches on a ~115 KB arena. This introduces src/memory/MemClass.h: a single MESHTASTIC_MEM_CLASS (TINY / SMALL / MEDIUM / LARGE) ranked by usable app heap after platform overheads, with the deliberate property that an unclassified chip lands in SMALL - a new target boots with small caches until someone opts it up in one visible place. The TMM cache, warm store, MAX_RX_TOPHONE and MAX_SATELLITE_NODES ladders in mesh-pb-constants.h now key off the class; branches pinned by something other than RAM stay explicit and say why (nRF52840's SoftDevice arena, RP2040's warm.dat watchdog bound). MAX_NUM_NODES intentionally stays separate - it is flash-shaped (nodes.proto vs LittleFS), not heap-shaped. A per-class MESHTASTIC_BOOT_CACHE_BUDGET static_assert now covers the three big boot-allocated caches, so the next cache-adding PR that would blow a small platform's budget fails to compile instead of exhausting heap in the field. No values change for any existing target: rak4631, tbeam, rak11310 and wio-e5 build byte-identical before/after; all ladders remain #ifndef-guarded so variant overrides keep working. * Address review: fix RP2350 class-table doc, add PacketRecord static_assert - MemClass.h's class table claimed RP2350 was MEDIUM while the mapping ladder classifies it SMALL (with RP2040) - the table now matches the ladder, with a note that RP2350 is a MEDIUM candidate whenever someone wants to tune it up (kept SMALL here so this header stays a behavioral no-op). - The boot-cache budget comment referenced a static_assert pinning PacketHistory::PacketRecord at 20 B that did not exist (only a layout comment). Add the real static_assert so the budget math in mesh-pb-constants.h fails to compile if the record layout changes. Also merges develop (the base #10898 landed there as a squash, which is what made this stacked branch conflict); develop's mesh-pb-constants.h is byte-identical to this branch's base, so the resolution keeps the MemClass ladder unchanged. rak4631 and wio-e5 build green; test_packet_history 47/47. * Address review: share PACKETHISTORY_MAX, trim policy comments - Hoist PACKETHISTORY_MAX from PacketHistory.cpp into mesh-pb-constants.h (next to the MAX_NUM_NODES it derives from) so the constructor clamp and the boot-cache budget static_assert use one definition instead of hand-mirrored arithmetic that could drift. The expression stays valid where MAX_NUM_NODES resolves at runtime (ESP32-S3, portduino); the pointless 2.0 double math becomes integer. - Trim the MemClass.h header (36 -> 16 comment lines) and the budget / sizing-policy comments per the repo comment-length guideline, keeping the class table, the fail-safe-small rule, the override mechanism, and the include-order constraint. rak4631 (compile-time MAX_NUM_NODES) and heltec-v3 (runtime) build green; test_packet_history 47/47.
54 lines
2.5 KiB
C
54 lines
2.5 KiB
C
#pragma once
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// Central memory-class ladder: RAM-sized caches key their per-platform tier off
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// MESHTASTIC_MEM_CLASS. Classes rank *usable app heap after platform overheads*
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// (SoftDevice, WiFi+BLE stacks) - not raw RAM - and an unclassified chip lands in
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// SMALL on purpose: small caches are a recoverable default, an exhausted heap is not.
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//
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// MEM_CLASS_TINY <32 KB free heap STM32WL
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// MEM_CLASS_SMALL ~100-250 KB nRF52840, classic ESP32/S2/C3, RP2040/RP2350
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// MEM_CLASS_MEDIUM ~250-500 KB, no PSRAM ESP32-S3/C6/P4 without PSRAM
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// MEM_CLASS_LARGE PSRAM or host ESP32-S3+PSRAM, portduino
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//
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// Compare ordinally (>=). RP2350 rides with RP2040 so this header stays a behavioral
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// no-op (MEDIUM candidate later). Variants may predefine MESHTASTIC_MEM_CLASS or any
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// cache constant - consumer ladders stay #ifndef-guarded. MAX_NUM_NODES is deliberately
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// unclassed (flash-shaped: nodes.proto vs filesystem). Included before configuration.h,
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// so only toolchain/board -D macros and the ARCH_* macros the ladders already use are
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// safe here.
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#define MEM_CLASS_TINY 1
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#define MEM_CLASS_SMALL 2
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#define MEM_CLASS_MEDIUM 3
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#define MEM_CLASS_LARGE 4
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#ifndef MESHTASTIC_MEM_CLASS
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#if defined(ARCH_STM32WL)
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#define MESHTASTIC_MEM_CLASS MEM_CLASS_TINY
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#elif (defined(CONFIG_IDF_TARGET_ESP32S3) && defined(BOARD_HAS_PSRAM)) || defined(ARCH_PORTDUINO)
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#define MESHTASTIC_MEM_CLASS MEM_CLASS_LARGE
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#elif defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32P4)
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#define MESHTASTIC_MEM_CLASS MEM_CLASS_MEDIUM
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#else
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// Classic ESP32 / S2 / C3, all nRF52, RP2040/RP2350, and - by design - any chip
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// nobody has classified yet: small caches are a recoverable default, an
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// exhausted heap is not. New RAM-rich targets opt up by adding a branch above.
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#define MESHTASTIC_MEM_CLASS MEM_CLASS_SMALL
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#endif
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#endif // MESHTASTIC_MEM_CLASS
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// Ceiling for the boot-allocated mesh caches (TMM + warm store + packet history);
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// mesh-pb-constants.h static_asserts their sum, so an oversized cache fails the build.
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// Raising a budget is allowed - as a visible, reviewable one-line diff.
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#ifndef MESHTASTIC_BOOT_CACHE_BUDGET
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#if MESHTASTIC_MEM_CLASS <= MEM_CLASS_TINY
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#define MESHTASTIC_BOOT_CACHE_BUDGET (8 * 1024)
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#elif MESHTASTIC_MEM_CLASS == MEM_CLASS_SMALL
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#define MESHTASTIC_BOOT_CACHE_BUDGET (16 * 1024)
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#elif MESHTASTIC_MEM_CLASS == MEM_CLASS_MEDIUM
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#define MESHTASTIC_BOOT_CACHE_BUDGET (32 * 1024)
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#else
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#define MESHTASTIC_BOOT_CACHE_BUDGET (256 * 1024)
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#endif
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#endif // MESHTASTIC_BOOT_CACHE_BUDGET
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